The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). The ICs are usually formed using both P-channel and N-channel FETs and the IC is then referred to as a complementary MOS or CMOS circuit. Certain improvements in performance of FET ICs can be realized by forming the FETs in a thin layer of semiconductor material overlying an insulator layer. Such semiconductor on insulator (SOI) FETs, for example, exhibit lower junction capacitance and hence can operate at higher speeds.
The MOS transistors formed in and on the SOI layer are interconnected to implement the desired circuit function. A number of voltage busses are also connected to appropriate devices to power those devices as required by the circuit function. The voltage busses may include, for example, a Vdd bus, a Vcc bus, a Vss bus, and the like, and may include busses coupled to external power sources as well as busses coupled to internally generated or internally altered power sources. As used herein, the terms will apply to external as well as internal busses. As various nodes in the circuit are either charged or discharged during the operation of the circuit, the various busses must source or sink current to those nodes. Especially as the switching speed of the integrated circuits increases, the requirement of sourcing or sinking current by a bus can cause significant voltage spikes on the bus because of the inherent inductance of the bus. To avoid logic errors that might be caused by the voltage spikes, it has become commonplace to place decoupling capacitors between the busses. For example, such decoupling capacitors can be connected between the Vdd and Vss busses. These decoupling capacitors are typically distributed along the length of the busses. The capacitors are usually formed as MOS capacitors with one plate of the capacitor formed by the same material used to form the gate electrode of the MOS transistors, the other plate of the capacitor formed by an impurity doped region in the SOI layer, and the dielectric separating the two plates of the capacitor formed by the gate dielectric.
One problem that can affect the yield and reliability of the integrated circuit can occur when using such MOS capacitors as the decoupling capacitors between two different voltage busses. The problem occurs because sufficient charge can build up on the capacitor to cause a destructive discharge through the capacitor dielectric material. This problem becomes more severe as device sizes shrink and especially as the thickness of the gate dielectric layer is reduced. The ability of the capacitor dielectric to withstand a charge build up is reduced as the thickness of the dielectric layer is reduced. The charge build up results from one or more of the plasma etching steps that are used to etch the interlayer dielectric materials and the metals used in the final steps in fabricating the integrated circuits.
Accordingly, it is desirable to provide a method for fabricating MOS devices that avoids the destructive effects of charge build up on decoupling capacitors. In addition, it is desirable to provide a method for fabricating an SOI device that incorporates decoupling capacitors. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.